3D Wafer Level Packaging

摘要

IC packaging continues to be driven to miniaturization not only in footprint (area of board space used) but also in package thickness or height. Reducing package thickness requires creating a thinner wafer or chip and a new concept of vertical integration of chips. The main technical obstacle to mass production of high density 3D modules is the challenge of forming die interconnections within a vertical stack. A manufacturer currently has to link them over the die edges; these over-edge interconnections are more art than science, and are barely automated, unreliable, and extremely cost-inefficient. A new Thru-Silicon manufacturing technology, based on Atmospheric Downstream Plasma (ADP) etching, allows for the interconnection of two or more wafers in a vertical stack The ADP thinning process provides, in one step, not only thinner wafers but also back-side contacts. The natural etch selectivity of ADP processing allows for the simple formation of Thru-Silicon interconnections. Process results and plans for 3D WLP stacks composed of memory, processors, control logic, and sensors for a wide variety of applications are presented.