SIMULATION OF THE RESPONSE OF EXTERNAL ESD PROTECTION CIRCUITS FOR CMOS ICS

摘要

CMOS ICs are highly susceptible to electrostatic discharge (ESD) induced voltage/current stresses. The IC manufacturer provides an on-chip protection circuit for improving the ESD susceptibility threshold of CMOS devices. However, device failures continue to occur due to electrical overstress (EOS) or due to ESD. For example, the device CD4050B has a built in immunity level of 2kV for the Human Body Model (HBM) ESD waveform. Hence the EOS/ESD failures noticed in these devices may be either due to a HBM-ESD stress level which is higher than 2kV or due to other types of work practice / area related ESD stress waveform. Thus, mere appears to be a need for providing external ESD protection circuits such that the device performance is not affected adversely. This paper gives an account of studies made , using SPICE and MC4 circuit simulation softwares, to determine the effectiveness of some of the external protection circuits to HBM-ESD.