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GATE DRIVER AND DISPLAY DEVICE HAVING THE SAME

机译:栅极驱动器和具有该栅极驱动器和栅极驱动器的显示设备

摘要

The gate driving circuit includes a plurality of stages each outputting a plurality of gate signals and a plurality of gate initialization signals. The N-th stage (where N is a natural number) outputs an N-th carry signal based on the input signal and provides a carry generation block, an input signal, and an input enable that provides the N-th carry signal to the N+1-th stage Receives a first output block outputting an N-th gate initialization signal and an N-th gate initialization signal based on an input disable signal that is an inverted signal of a signal and an input enable signal, and receives the N-th gate initialization signal depending on the N-th gate initialization signal and a second output block for outputting the Nth gate signal delayed by one horizontal period to the Nth gate initialization signal output. Gate signals and gate initialization signals are selectively output based on the input enable signal and the input disable signal.
机译:栅极驱动电路包括多个级,每个级输出多个栅极信号和多个栅极初始化信号。第N级(其中N是自然数)基于输入信号输出第N进位信号,并提供进位生成块、输入信号、,以及向N+1级提供第N进位信号的输入使能接收第一输出块,该第一输出块基于作为信号和输入使能信号的反转信号的输入禁用信号输出第N栅极初始化信号和第N栅极初始化信号,以及接收取决于第N栅极初始化信号的第N栅极初始化信号和用于将延迟一个水平周期的第N栅极信号输出到第N栅极初始化信号输出的第二输出块。基于输入使能信号和输入禁用信号选择性地输出栅极信号和栅极初始化信号。

著录项

  • 公开/公告号KR102383363B1

    专利类型

  • 公开/公告日2022-04-07

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR1020150144831

  • 发明设计人 박수형;안태형;

    申请日2015-10-16

  • 分类号G09G3/20;G09G3/32;G09G3/36;

  • 国家 KR

  • 入库时间 2024-06-14 22:59:29

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