The gate driving circuit includes a plurality of stages each outputting a plurality of gate signals and a plurality of gate initialization signals. The N-th stage (where N is a natural number) outputs an N-th carry signal based on the input signal and provides a carry generation block, an input signal, and an input enable that provides the N-th carry signal to the N+1-th stage Receives a first output block outputting an N-th gate initialization signal and an N-th gate initialization signal based on an input disable signal that is an inverted signal of a signal and an input enable signal, and receives the N-th gate initialization signal depending on the N-th gate initialization signal and a second output block for outputting the Nth gate signal delayed by one horizontal period to the Nth gate initialization signal output. Gate signals and gate initialization signals are selectively output based on the input enable signal and the input disable signal.
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