Apparatus comprising: a single chip network, NoC (10; 300) having a plurality of caching agents (310x) coupled by an interconnect fabric (50; 320) and a plurality of Routers (100; 300) each having a plurality of virtual channels (110a-110n), a switch (130) and criticality logic (120); each of the plurality of virtual channels (110a-110n) comprising: an input multiplexer (112) for receiving cache coherency messages, each of the cache coherency messages having a criticality indicator associated therewith; a plurality of queues (115a) 115n) coupled to the input multiplexer (112) for storing the cache coherency messages, each of the queues (115 "-115") being associated with at least one of the criticality indicators; and an output multiplexer (118) coupled to the plurality of queues (115a-115n) for selecting an output of one of the queues (115a-115n) based at least in part on the corresponding criticality indicator; wherein the switch (130) connects to the Plurality of virtual channels (110a-110n) is coupled to output the cache coherence messages to the interconnect structure (50), and the criticality logic (120) maps a cache coherence message to a criticality indicator and the criticality indicator to a header of each packet of the Appends cache coherence message, wherein the criticality indicator indicates a relative criticality of a cache coherence message with respect to a set of cache coherence messages and wherein the criticality logic (120) is associated with a table for mapping each of the set of cache coherence messages to a criticality indicator, wherein the criticality logic (120) is mapping without a software H instruction carried out by a user.
展开▼
