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SEMICONDUCTOR MEMORY DEVICE OUTPUTTING READY BUSY SIGNAL AND MEMORY SYSTEM INCLUDING THE SAME

机译:半导体存储器件输出现成忙信号和内存系统,包括相同

摘要

A semiconductor memory device according to an embodiment of the present invention is configured to control memory cells, operates in a first mode capable of communicating with an external device when the chip select signal is enabled, and communicates with the external device when the chip select signal is disabled. a peripheral circuit operating in a non-communicating second mode, and a ready busy signal generator configured to bias the ready busy line according to whether the peripheral circuit has a ready or busy state when the chip select signal is enabled. .
机译:根据本发明的实施例的半导体存储器件被配置为控制存储器单元,在能够与外部设备启用时能够与外部设备通信的第一模式,并在芯片选择信号时与外部设备通信 被禁用。 在非传送的第二模式下操作的外围电路,以及被配置为在启用芯片选择信号时的外围电路是否具有就绪或忙碌状态的现成忙线的现成忙信号发生器。 。

著录项

  • 公开/公告号KR102291639B1

    专利类型

  • 公开/公告日2021-08-20

    原文格式PDF

  • 申请/专利权人 에스케이하이닉스 주식회사;

    申请/专利号KR20150099188

  • 发明设计人 정재형;김광현;

    申请日2015-07-13

  • 分类号G11C7/10;G11C16/32;G11C7/22;

  • 国家 KR

  • 入库时间 2022-08-24 22:18:10

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