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SEMICONDUCTOR MEMORY DEVICE OUTPUTTING READ-BUSY SIGNAL AND MEMORY SYSTEM INCLUDING THE SAME

机译:半导体存储器输出包括相同信号的忙/闲信号和存储器系统

摘要

A semiconductor memory device includes a plurality of memory cells; a peripheral circuit suitable for controlling the memory cells, and operating in first and second modes respectively corresponding to enablement and disablement of a chip selection signal; and a ready-busy signal generator suitable for biasing a ready-busy line according to whether the peripheral circuit is in a ready or busy state during the enablement of the chip selection signal. Communication between the semiconductor memory device and an external device is allowed in the first mode. The communication between the semiconductor memory device and the external device is not allowed in the second mode.
机译:半导体存储装置包括:多个存储单元;以及多个存储单元。外围电路,其适于控制存储器单元,并且分别在第一模式和第二模式下操作,分别对应于芯片选择信号的启用和禁用;就绪信号发生器,用于根据在启用芯片选择信号期间外围电路是处于就绪状态还是处于繁忙状态来偏置就绪总线。在第一模式下,允许半导体存储装置与外部装置之间的通信。在第二模式下,不允许半导体存储装置与外部装置之间的通信。

著录项

  • 公开/公告号US2017018296A1

    专利类型

  • 公开/公告日2017-01-19

    原文格式PDF

  • 申请/专利权人 SK HYNIX INC.;

    申请/专利号US201514967621

  • 发明设计人 JAE HYEONG JEONG;KWANG HYUN KIM;

    申请日2015-12-14

  • 分类号G11C8/06;G11C7/10;G11C7/22;

  • 国家 US

  • 入库时间 2022-08-21 13:48:56

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