Multi-dimensional integrated chip design and manufacturing processes using wafer stacking techniques

摘要

This disclosure concerns a process for the creation of a multi-dimensional integrated chip design.In some designs, the process can be performed by bonding a second substrate to a surface of a first substrate.There will be a first edge rim section along a first loop and up to a first circumference section of thesecond substrates carried in.A second edge rim section is carried out along a second loop and up to a second circumference section of the second substrate and into the first substrate.A third edge rim section is carried out along a third loop and up to a third circumference section of the first substrate.