首页> 外国专利> Connectivity verification for flip-chip and advanced packaging technologies

Connectivity verification for flip-chip and advanced packaging technologies

机译:倒装芯片和先进包装技术的连接验证

摘要

The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.
机译:故障检测系统提供了一种有效的方法,用于使用芯片测试电路和芯片组件在电子封装中测试和监视元件连接的组件连接,这减少了对外部测试设备和分析的需求。 芯片性质允许通过确定芯片参考测量并使用参考测量来确定包装的芯片参考测量来在电子包装的组装过程中以及在使用电子包装期间的实时测试。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号