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Silicon carbide epitaxial wafer, silicon carbide insulated gate bipolar transistor, and manufacturing method thereof

机译:碳化硅外延晶片,碳化硅绝缘栅双极晶体管及其制造方法

摘要

PROBLEM TO BE SOLVED: To provide a SiC-IGBT arranged so that the occurrence of expansion of a lamination defect attributed to excessive electron injection in the vicinity of a collector electrode can be suppressed effectively during a time when IGBT arranged by use of a self-supporting epitaxial film is in a forward operation.SOLUTION: An SiC-IGBT comprises: a p-type collector layer (p-type buffer layer 2); an ntype voltage sustaining layer 4 provided over the collector layer; p-type base regions (p-type second base regions 6a, 6b) provided over an ntype voltage sustaining layer 4; ntype emitter regions 8a, 8b provided over the p-type base regions; a gate insulative film 10 provided over the voltage sustaining layer 4; and a gate electrode 11 provided on the gate insulative film 10. The p-type buffer layer 2 has a thickness t1 of 5 μm or more and 20 μm or less, and is added with Al at an impurity concentration of 5×10cmor more and 5×10cmor less, and B at an impurity concentration equal to or more than 2×10cmand less than 5×10cm.SELECTED DRAWING: Figure 1
机译:要解决的问题:提供一个SiC-IGBT,其布置成使得在通过使用自动排列的IGBT布置的IGBT的时间期间,可以在收集电极附近抑制归属于电极附近的层压缺陷的膨胀的发生。支撑外延膜处于正向操作。SIC-IGBT包括:P型集电极层(P型缓冲层2);在集电极层上提供的NTYPE电压维持层4; p型基区(P型第二基区6a,6b)提供在NTYPE电压维持层4上; NTYPE发射器区域8a,8b提供在p型基区;提供在电压维持层4上的栅极绝缘膜10;和设置在栅极绝缘膜10上的栅电极11. p型缓冲层2的厚度T1为5μm以上且20μm或更小,并以5×10cmor的杂质浓度为5×10cmor较少5×10cmor,B处于杂质浓度等于或大于2×10cmand小于5×10cm.选择图:图1

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