SEMICONDUCTOR PACKAGE WITH A SILICON CARBIDE POWER SEMICONDUCTOR CHIP DIFFUSION SOLDERED TO A COPPER LEADFRAME PART AND A CORRESPONDING MANUFACTURING METHOD

摘要

A semiconductor package (100) comprises a power semiconductor chip (110) comprising SiC, a leadframe part (120) comprising Cu, wherein the power semiconductor chip (110) is arranged on the leadframe part (120), and a diffusion solder joint (130) electrically and mechanically coupling the power semiconductor chip (110) to the leadframe part (120), wherein the diffusion solder joint (130) comprises at least one intermetallic phase. A method for fabricating a semiconductor package (100) comprises: providing a SiC semiconductor wafer (200) comprising a plurality of power transistor circuits (210); depositing a first metal layer (220) on the SiC semiconductor wafer (200); singulating the SiC semiconductor wafer (200) into individual power semiconductor chips (110), each power semiconductor chip (110) comprising at least one power transistor circuit (210); providing a leadframe part (120) comprising Cu; arranging at least one of the power semiconductor chips (110) on the leadframe part (120) such that the first metal layer (220) faces the leadframe part (120); and diffusion soldering the at least one power semiconductor chip (110) to the leadframe part (120) such that the first metal layer (220) and the leadframe part (120) form a diffusion solder joint (130) comprising at least one intermetallic phase. One or more additional metal layers (402, 404, 406, 408) may be arranged between the power semiconductor chip (110) and the first metal layer (220), having various functions, for example, configured as diffusion barrier, seed layer, adhesion layer, etc. For example, a stack of a first additional layer (402) of e.g. TiSi, a second additional layer (404) of e.g. NiV, an optional third additional layer (406) of e.g. Al and a fourth additional layer (408) of e.g. Ti may be provided between the power semiconductor chip (110) and the first metal layer (220).