Contact etching and metallization to improve LED device performance and reliability

摘要

Light emitting device 200 includes vertical vias 280 through P-type semiconductor layer 140 and active layer 130. By using vertical vias, quantum well damage is reduced, allowing the PN space 278 to be shortened and the reflective surface 150 to be increased. A dielectric structure 250 is formed in the via resulting in an angled wall 255 extending to the upper surface of the device. Other dielectric structures cover the upper surface and the sloped wall to provide selective contact to the semiconductor layer. Subsequently, a metal layer is applied. The metal layer does not provide a vertical drop since the dielectric structure provides a continuous slope from the surface of the device. Since the active layer does not extend into the via, the contact to the N-type semiconductor layer can be located close to the wall of the via, which can increase the area available for the reflective layer.