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On-die circuitry for electrostatic discharge protection (ESD) analysis

机译:用于静电放电保护(ESD)分析的模具电路

摘要

Some embodiments include apparatuses having an electrostatic discharge (ESD) protection circuit coupled to a node, and first, second, and third circuits coupled to the node. The first circuit includes a first charge pump to cause a voltage at the node during activation of the first circuit to change from a first voltage value to a second voltage value within first multiple periods of a clock signal, the second voltage value being less than the first voltage value. The second includes a second charge pump to cause a voltage at the node during activation of the second circuit to change from a third voltage value to a fourth voltage value during second multiple periods of the clock signal, the fourth voltage value being greater than the third voltage value. The third circuit generates information based on the values of the voltage at the node during activation of the first and second circuits. The apparatuses optionally include a fourth circuit to generate an additional voltage at an additional node. The additional voltage has a negative voltage value. The additional node is coupled to a gate of at least one transistor of the first circuit.
机译:一些实施例包括具有耦合到节点的静电放电(ESD)保护电路的装置,以及耦合到节点的第一,第二和第三电路。第一电路包括第一电荷泵,以在激活第一电路期间在节点处导致电压从第一电压值改变到时钟信号的第一多个周期内的第二电压值,第二电压值小于第一电压值。第二电荷泵包括第二电荷泵,以在第二电路的激活期间在节点期间导致节点的电压从第三电压值在时钟信号的第二多个周期期间从第三电压值改变到第四电压值,第四电压值大于第三个电压值电压值。第三电路基于在第一和第二电路的激活期间基于节点处的电压的值来产生信息。该装置可选地包括第四电路以在附加节点处产生附加电压。附加电压具有负电压值。附加节点耦合到第一电路的至少一个晶体管的栅极。

著录项

  • 公开/公告号US10944256B2

    专利类型

  • 公开/公告日2021-03-09

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201815939807

  • 发明设计人 HARRY MULJONO;HORAIRA ABU;LINDA K. SUN;

    申请日2018-03-29

  • 分类号H02H9/04;H01L27/02;

  • 国家 US

  • 入库时间 2022-08-24 17:34:07

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