PULSE-TRAIN FORMING CIRCUITS

摘要

1308784 Transistor pulse circuits SIEMENS AG 24 Sept 1970 [25 Sept 1969] 45428/70 Heading H3T A pulse train forming circuit for producing separate output pulse trains having repetition rates which are suitable for the subsequent production of an even-numbered and an oddnumbered multiple of a given frequency f 0 comprises a pulse shaping stage IP, Fig. 1, a monostable stage MM, a bi-stable stage FF, AND gates G1, G2, an inverter U and amplifier stages V1 and V2 providing an output pulse train T (2f 0 ) (a, Fig. 3, not shown) of double the given frequency (f 0 ) and an output pulse train (c, Fig. 5, not shown) whose repetition frequency for pulses of one polarity is equal to the given frequency T(f 0 ) respectively in response to a sinusoidal input frequency 2f 0 that is double the given frequency. The pulse shaping circuit IP delays the input (b, Fig. 2, not shown) to the monostable stage MM with respect to the input (a, Fig. 2, not shown) applied to the bi-stable stage FF. The output T(f 0 ) (a, Fig. 4, not shown) from the bi-stable stage FF, which divides its input by two, prepares each of the AND gates G1, G2 before arrival of the pulses (b, Fig. 4, not shown) from the monostable stage MM at a frequency T(2f 0 ). The output pulse trains (c, Fig. 4, not shown) of frequency T(2f 0 ) from the gates G1, G2 are displaced from one another by the time which corresponds to the period (2f 0 ). The output pulses from the gate G1 are inverted (b, Fig. 5, not shown) by inverter U and combined with the pulse train (a, Fig. 5, not shown) from the gate G2 in amplifier V2 so that a pulse train of opposite polarity pulses (c, Fig. 5, not shown) is obtained at the output of the amplifier V2 suitable for the production of odd numbered multiples of the basic frequency (f 0 ). The output pulse train T(2f 0 ) (a, Fig. 3, not shown) from the amplifier V1 is suitable for the production of even numbered multiples of the basic frequency. In a transistor arrangement of Fig. 1, shown in Fig. 6, the pulse shaper IP is Ts1, Ts7, Ts13, the monostable stage MM is Ts2, Ts8, Ts9, the bi-stable stage FF is Ts11, Ts12, the AND gates G1 and G2 are Ts3, Ts5 and Ts4, Ts6 and the inverter U is Ts10. The input transistor Ts1 acts to clip and amplify the input sinusoidal signal. The output amplifiers include push-pull Class B output stages Ts14, Ts18 and Ts17, Ts20 including driven transistors Ts15, Ts19 and Ts16. The circuit can be of integrated circuit form.