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integrated circuit design technology was in a field effect memory circuit, including a transistor with elements
integrated circuit design technology was in a field effect memory circuit, including a transistor with elements
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机译:集成电路设计技术是在场效应存储电路中,包括带有元件的晶体管
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1441004 Semi-conductor devices SIEMENS AG 15 Oct 1973 [13 Nov 1972] 48507/73 Heading H1K An integrated storage circuit comprises a number of single field-effect transistor storage elements each having a gate electrode 5, disposed in a first plane above the surface of the circuit and spaced therefrom by a first insulating layer 4, the gate electrode 5 of at least some of the transistors being connected to a common conductor path 7 lying in a second plane spaced above the first plane by a second insulating layer 44, the contact region between each gate electrode 5 and the common conductor 7 being located at least in part above the channel zone 8 of the respective IGFET. As shown, each transistor storage element in the substrate 1 has diffused drain and source regions 2, 3 and a first layer 4 of silicon dioxide formed thereon. Gate eletrode 5 and an electrode 6 are formed of doped polycrystalline silicon or molybdenum and the common conductor path 7 of aluminium is formed over a second layer 44 of silicon dioxide. Each of the single-transistor storage elements in the storage circuit may be connected in series with a respective dielectric capacitor whose electrodes are formed by the electrode 6 in the first conductor plane and the inversion layer 66 in the semi-conductor body. The integrated storage circuit may be formed by an array of storage elements connected in rows, Fig. 3 (not shown).
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机译:1441004半导体器件SIEMENS AG 1973年10月15日[1972年11月13日]标题H1K集成存储电路包括多个单个场效应晶体管存储元件,每个存储元件具有栅电极5,布置在表面上方的第一平面中在电路的一部分中,其通过第一绝缘层4与之隔开,至少一些晶体管的栅电极5连接至位于第二平面中的公共导体路径7,该第二平面在第一平面上方被第二绝缘层44隔开,每个栅电极5和公共导体7之间的接触区至少部分位于相应IGFET的沟道区8上方。如图所示,衬底1中的每个晶体管存储元件具有扩散的漏极和源极区2、3以及在其上形成的二氧化硅的第一层4。栅电极5和电极6由掺杂的多晶硅或钼形成,并且铝的公共导体路径7形成在二氧化硅的第二层44上。存储电路中的每个单晶体管存储元件可以与相应的介电电容器串联连接,该介电电容器的电极由第一导体平面中的电极6和半导体主体中的反型层66形成。集成存储电路可以由图3中未示出的成行连接的存储元件的阵列形成。
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