A generalized and modular logic system for all arithmetic/logical units of a digital computer. Each arithmetic/logical unit of a computer is partitioned into sections formed of combinational logic networks and storage circuitry. The storage circuitry is sequential in operation and employs clocked dc latches. Two or more synchronous, non-overlapping, independent system clock trains are used to control the latches. A single-sided delay dependency is imparted to the system. The feedback connections from the respective latch circuitry are made through combinational logic to other latch circuitry that has a system clock other than the system clock acting on the initiating latch circuitry. With each latch, there is provided additional circuitry so that each latch acts as one position of a shift register having input/output and shift controls that are independent of the system clocks and the system inputs/outputs. All of the shift register latches are coupled together into a single shift register.
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