The carry cn or inverted carry cnx of the n'th place and the derived inverted carry cnx or cn delayed by between two and four gate transit times are linked together in a logic element to form a part signal according to an AND function and all the part signals are combined according to an OR function. To delay the carries or their conditional fractions, the transit times are used in the logic elements of the adding circuit. Use of the carry transit signal to control the addition time gains time and ensures that addition is completed even if the adder has extremely slow gates in comparison with the typical gate transit time.
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