IMPROVEMENTS IN OR RELATING TO ELECTRIC IMPULSE TRANSMITTERS

摘要

1369829 Impulse transmitters STANDARD TELEPHONES & CABLES Ltd 23 Dec 1971 59927/71 Heading H4K Ooding means translates the decimal digits of a directory telephone number into binary form and enters them into successive stages of a circulating store comprising at least one cyclically connected shift register, the digits being read out one by one to a counter which controls the output from an impulse generator, thereby to produce an impulse train corresponding to the digit read-out. A single second shift register having the same number of stages as the, or each, register of the store is used to circulate a marker pulse which controls the read in and read out of the store. The circuit to be described may be formed on integrated circuit chips, the active components being preferably F.E.T.'s. The shift registers BS1-BS4 (Fig. 2) and MPR (Fig. 3) associated with the store and marker pulse respectively are each of eighteen stages and are driven by 20 KHz clock pulses. When a non-locking key or board KB is depressed a four bit coded signal appears at one input of And gates IG5-IG8 and a signal COM switches bi-stable BC1, Fig. 3, via an antibounce circuit AB which reduces the effects of the bounce of contact SC6. Providing a signal DL indicating a data word in the eighteenth position of the store is not present at inverter gate 12, And gate AG2 is opened when the marker pulse in MPR next reaches stage eighteen. A control pulse G1P is then applied to And gates IG5-IG8 and the four bit coded signal is fed into stage 1 of the store. The signal GIP inhibits and gate AG1 via inverter gate I1 and the marker pulse is fed back into register MPR via a delay circuit BD1 which delays the marker pulse by one clock pulse interval. This ensures that when the marker pulse is next in the eighteenth stage, the previously stored data signal is in stage one of the store. On the next clock pulse, the data signal moves to stage two of the store and if a button is depressed the next data signal is read in to stage 1, the marker pulse again being delayed by one clock pulse so as to be one stage behind the last stored signal. If a data signal is present in the eighteenth stage of the store when the marker pulse is present in the eighteenth stage of register MPR, the store is full and a pulse DL disables And gate AG2 via inverter 12, thereby preventing further digits from being read into the store. The control pulse GIP also sets bi-stable BC3, Fig. 4, the output of which together with a signal CTRZ, which indicates that counter CTR, Fig. 2, is in the zero state, and a signal CP, derived from the output of an impulse generator involving shift register WG, Fig. 4, is applied to an And gate AG4, the presence of all three signals switching bi-stable BC4. The output of bi-stable BC3 also energizes a relay ONR which is used to prepare the outpulsing path of the telephone set for the transmission of loopdisconnect impulses. When the marker pulse in shift register MPR occurs in stage seventeen a signal pulse PP is produced. If this coincides with the presence of a stored signal in stage eighteen of the store signals PP and DL occur simultaneously and with bi-stable BC4 set and bi-stable BC6 reset And gate AG5 is opened setting bi-stable BC5 whose output is fed after a delay determined by circuit BD2 to And gate AG6, the delay being such that the signal in store stage eighteen has moved to stage one before the signal reaches And gate AG6. When a signal is next present in stage eighteen of the stote the signal DL opens gate AG6 and a signal pulse GD is applied to gates OG1-OG4 and CAG1-CAG4. The stored signal in stage eighteen is therefore prevented from returning to stage one of the store and is fed to step the counter CTR. Signal GD also sets bi-stable BC6, and And gate AG8 is opened whenever a bi-stable BC2 is set. Bi-stable BC2 is arranged to switch on and off at a rate of ten times per second with the correct mark to space ratio for a dialling pulse train in a manner to be described and it feeds a relay DPR. The signal GD also resets bi-stables BC4 and BC5. The counter CTR is then stepped towards its zero state by signal CP which is of the same frequency as the pulses supplied to relay DPR. During this time further stored signals are prevented from being fed to the counter as the And gate AG5 has a zero input due to bi-stable BC6 being set. When the counter reaches the zero state the signal CTRZ reappears and it inhibits And gate CAG via inverter 14, thereby stopping the counter. The signal CTRZ is also applied to And gate AG7 which supplies a signal GP after delay determined by circuit BD3 to reset bi-stable BC6. And gate AG8 is therefore closed and the transmission of pulses to the relay is stopped. The signal GP is also used to set the counter CTR to a predetermined state. The time in which the counter counts down to the zero state from this state determines the interdigital pause. The absence of signal CTRZ during this time from gate AG4 prevents further read out of stored signals to the counter during the pause. When the counter reaches the zero stage gate AG4 will again open and bi-stable BC4 will be set. When next there is a coincidence between the seventeenth stage of the marker register and the eighteenth stage of the store the process repeats itself. If at any time there is not a coincidence bi-stable BC3 is reset via gate AG3, i.e. the store is empty. Bi-stable BC3 is only set again when signal GIP indicates a data signal has been inserted into store. The impulse generator is described and claimed in Specification 1,369,830 which is divided out of this Specification. Taking up or replacing the handset at any time resets, all the stores. The circuits may be powered by a local battery or a local battery rechargeable over the telephone line. Reference has been directed by the Comptroller to Specification 1,236,961.