HIGH SPEED COMPUTER PROGRAMMING DEVICE LARGELY REDUCING STORAGE CAPACITY

摘要

A main programming memory device is coupled to an arithmetic logic unit through controllable gating circuitry which permits the majority of control data within the main memory to be sequentially transmitted to the arithmetic logic unit for control of arithmetic data therein. An instruction designation source controls a main memory address device which in turn is coupled to the main programming memory to initiate data readout to the arithmetic logic unit, through the gating circuitry, such instruction designation source also being coupled to a function memory which contains arithmetic logic data unique to particular instructions to be executed. Data source selection bits are associated with arithmetic logic data stored within the main programming memory and control the gating circuitry to cause arithmetic logic data to be transmitted from the main programming memory to the arithmetic logic unit when the source selection bits have a first value, and which cause the unique instruction data within the addressed function memory to be transmitted to the arithmetic logic unit, rather than data from the main programming memory, when the source selection bits have a second value.