Method for forming a conductor line in an integrated semiconductor memory and an integrated semiconductor memory with cells including a capacitor and a field effect transistor

摘要

A bit line (46) for a dynamic random access memory (RAM) structure is formed of materials selected from the groups consisting of polycrystalline silicon, a metal silicide, and/or a metal. The polycrystalline silicon (40) contacts at least a portion of the drain region (37) of an FET in each of a plurality of cells of the RAM structure via a self-aligned contact. When the selected material is polycrystalline silicon (40) and a metal silicide (41), the conductor bit (46) line is continuous extending along the drain regions (37). When the method is selected, segments (56) of polycrystalline silicon, possibly covered by metal silicide, are formed and electrically connected to each other by overlapping metal segments (57).