High voltage IIL logic gate - has NPN transistor base to injection input, collector to output and emitter region at least as large as that of inverter transistor

摘要

The logic gate has an injection PNP transistor (T1) and an inverting NPN transistor. The collector and base of the PNP transistor (T1) are connected to the base and emitter of the NPN transistor (T2) respectively. The injected current is fed into the emitter of the PNP transistor (T1) and a logic signal is input into the base of the NPN transistor (T2). In this operator, another NPN transistor (T3) is added, and its base is connected to the injecting input. The emitter is connected to one collector of the original NPN transistor (T2) and its collector forms the output of the operator. The emitter surface of this additional NPN transistor (T3) is at least as large as the emitter surface of the original NPN transistor (T2).