Digital phase-locked loop for synchronisation on reception of binary signals

摘要

On the basis of known DPLL circuits (Digital Phase-locked loop), comprising a cycle counter (Z), a phase detector (ECPD), a forward/backward counter (VRZ) and a control circuit (I/D) connected in front of the cycle counter (Z) for insertion or extraction of one of the clock pulses for the cycle counter (Z) so that the latter is incremented in accelerated or delayed fashion and a phase correction thereby effected, the direct evaluation of binary data signals with varying frequencies is possible due to an additional bistable trigger circuit (BK) and a novel combination of the alternating input and output signals (DAT and SYN-T) to control the forward/backward counter (VRZ) so that, using simple means, binary data signals with different coding can be directly evaluated. (FIG.1) IMAGE