Digital generator producing clock signal of period proportional to received binary number, comprising components connected in series in phase-locked loop

摘要

The generator comprises a digital oscillator producing a clock signal (CKHF) on the basis of N logic signals S(1), S(2), ..., S(N) representing a control number of N bits, where N is an integer greater than 1. The oscillator comprises N+1 components C(0), C(1), ..., C(N), where N components C(1), C(2), ..., C(N) of high weight are each affected by the proper weight i in the range from 1 to N, and the component C(0) of low weight delivers the clock signal, which is branched to the input (e) of component C(N). At least one component C(i) of high weight comprises two branches: the first branch with a cell (F) and an interrupter INTC1(i) connected in series, where the interrupter is controlled by the logic signal S(i) so that it is open when the signal is active; the second branch with a number NC(i)=2i+1 or cells (F) and an interrupter INTC2(i) connected in series, where the interrupter is controlled by the same logic signal so that it is closed when the signal is active. The low-weight component C(0) contains an even number of inverters if N is odd, or an odd number of inverters if N is even. Each cell (F) contains an odd number (NF) of inverters connected in series. At least one cell, or all cells, contains an interrupter (INTF) connected in series with the inverts. The oscillator also comprises means for applying a precharge signal to the cells of the two branches of component C(i). The precharge signal is the clock signal, or its inverse; or the input signal of component C(i). The generator also comprises a comparator for comparing the period of clock signal to a desired period and delivering a control number (NR) of N bits, so that the control number increases/decreases when the period of the clock signal is below/above the desired value, otherwise remains constant.