Digital registered data buffer for use in RAM memory system, has clock output of phase-locked loop providing clock signal shifted in phase by specific degree plus fraction of clock period with respect to feedback clock signal

摘要

The buffer has a clock output of a phase-locked loop providing a feedback clock signal for application to a feedback input of the loop. Another clock output provides a clock signal shifted in phase by a fraction of the clock period with respect to the feedback clock signal for application to a clock input (CLK) of a data register. A third clock output provides a clock signal shifted in phase by an amount of specific degree plus a fraction of the clock period with respect to the feedback clock signal for application to a clock input of a data destination device e.g. static dynamic RAM. An independent claim is also included for a memory system comprising a memory controller.