PHASE-LOCKED LOOP CIRCUIT OUTPUTTING CLOCK SIGNAL HAVING FIXED PHASE DIFFERENCE WITH RESPECT TO INPUT CLOCK SIGNAL

摘要

A phase-locked loop circuit includes a first PFD (phase detector) and a second PFD. The first PFD accepts an input clock signal CLK and a feedback clock signal FBCLK, and supplies its positive output to a charge pump. The second PFD accepts an inverted signal NCLK of the input clock signal CLK and the feedback clock signal FBCLK, and supplies its negative output to the charge pump. The phase-locked loop circuit outputs the clock signal whose phase differs from the phase of the input clock signal by 90 degrees.