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A circuit of the memory cells, has a transistor by bit

机译:存储单元的电路逐个具有晶体管

摘要

P the present invention relates to a circuit of memory cells to a transistor. / p & & p & in such a memory circuit comprising memory cells 10 used in two groups of rows 30 and 40, it is conventionally made of the differential amplifiers 12 having a first input 1 connected to the memory cells of the group 30 and a second input 2 connected to the memory cells of the unit 40. Such a circuit comprises an output amplifier 14, which conventionally one of the inputs 3 is connected to a potential of labels. According to the present invention, this input terminal 3 is connected to the cells of the second group by means of connection means 20 'controlled by the same control signals as those which commanded the connection means 20 of the conventional. Application to the increase of speed of the memory circuits. / p
机译:本发明涉及一种晶体管的存储单元的电路。 & &在这种包括在两组行30和40中使用的存储单元10的存储电路中,通常由差分放大器12制成,该差分放大器12具有连接到组30的存储单元的第一输入1和连接到组30的存储单元的第二输入2。单元40的存储单元。这种电路包括输出放大器14,其通常将输入3之一连接到标签电位。根据本发明,该输入端子3通过连接装置20'连接到第二组单元,连接装置20'由与命令常规连接装置20相同的控制信号控制。应用于增加存储电路的速度。

著录项

  • 公开/公告号FR2358725B1

    专利类型

  • 公开/公告日1984-05-18

    原文格式PDF

  • 申请/专利权人 NIPPON ELECTRIC CY LTD;

    申请/专利号FR19770021355

  • 发明设计人

    申请日1977-07-11

  • 分类号G11C11/40;H01L27/04;

  • 国家 FR

  • 入库时间 2022-08-22 08:46:37

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