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EXCLUSIVE LOGICAL SUM CIRCUIT

机译:独家逻辑求和电路

摘要

PURPOSE:To form a complementary exclusive logical sum circuit with a reduced number of the component element by containing three units of the first conductive MISFFT plus three units of the second conductive MISFFT and securing the mutual control with the input signal of the other side. CONSTITUTION:P-type MISFETQ3 and Q4 which are controlled by the signals of input terminal B and A of the other side are provided between input terminal A and B and output terminal X, and then n-type MISFETQ1 is installed between terminal X and reference potential terminal V2 to be controlled by the output signal of terminal X'. Then n-type MISFETQ5 and Q6 are provided between terminal A and B and terminal X', and P-type MISFETQ2 is installed between terminal X' and power source V1. When the levels of power source V1 and V2 are set to 1 and 0 respectively, FETQ5 and Q6 are turned on with Q4 and Q4 turned off respecitvely. At the same time, Q1 is turned on with Q2 turned off, and output X and X' become to the levels of 0 and 1 respectively. Thus, the output of exclusive OR is obtained at terminal X, and the output of exclusive NOR is obtained at terminal X' respectively. The action of this circuit is shown in the truth value table.
机译:目的:通过包含三个第一导电MISFFT单元和三个第二导电MISFFT单元,并确保与另一侧的输入信号的相互控制,来形成组成元素数量减少的互补异或逻辑电路。构成:在另一端的输入端子B和A的信号控制下的P型MISFETQ3和Q4设置在输入端子A和B与输出端子X之间,然后在端子X和基准之间安装n型MISFETQ1电位端子V2由端子X′的输出信号控制。然后,在端子A和B与端子X′之间提供n型MISFETQ5和Q6,并且在端子X′与电源V1之间安装P型MISFETQ2。当电源V1和V2的电平分别设置为1和0时,FETQ5和Q6打开,而Q4和Q4分别关闭。同时,Q1打开,Q2关闭,输出X和X'分别变为0和1的电平。因此,在端子X处获得异或的输出,并且在端子X′处获得异或的输出。真值表中显示了该电路的作用。

著录项

  • 公开/公告号JPS6038054B2

    专利类型

  • 公开/公告日1985-08-29

    原文格式PDF

  • 申请/专利权人 HITACHI LTD;

    申请/专利号JP19770122372

  • 发明设计人 KOBAYASHI ISAMU;TAKANASHI AKIRA;

    申请日1977-10-14

  • 分类号H03K19/0944;H03K19/0948;H03K19/21;

  • 国家 JP

  • 入库时间 2022-08-22 08:21:58

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