A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of CMOS inverters

摘要

The gate electrode (22a) of a first CMOS inverter is connected to the drains (18b, 18d) of each transistor of a second CMOS inverter via an interconnection (28b), and the gate electrode (22b) of the second CMOS inverter is connected to the drains (18a, 18c) of the first CMOS inverter via an interconnection (28b), to form a flip-flop circuit. A pair of transfer transistors (Qnl3, Qn14) are connected to the nodes of this flip-flop circuit. A plurality of memory cells each constituted by the flip-flop circuit and the pair of transfer transistors are integrated in a matrix form to form a semiconductor memory device. The pair of gate electrodes (22a, 22b) are formed of a first polycrystal-line silicon layer which includes an impurity of the first conductivity type. The pair of interconnections (28a, 28b) are formed of an impurity-doped second polycrystalline silicon layer (32a, 32b, 34a, 34b) and a high-melting point metal layer (36a, 36b) and formed on a first interlayer insulation film. The high-melting point metal layer is provided to prevent an increase in the resistance value due to the formation of a pn junction formed by the interconnections.