A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of CMOS inverters

摘要

The gate electrode of a first CMOS inverter is connected to the drains of each transistor of a second CMOS inverter via an interconnection, and the gate electrode of the second CMOS inverter is connected to the drains of the first CMOS inverter via an interconnection, to form a flip-flop circuit. A pair of transfer transistors are connected to the nodes of this flip-flop circuit. A plurality of memory cells each constructed by the flip-flop circuit and the pair of transfer transistors are integrated in a matrix form to form a semiconductor memory device. The pair of gate electrodes are formed of a first polycrystalline silicon layer which includes an impurity of the first conductivity type. The pair of interconnections are formed of an impurity-doped second polycrystalline silicon layer and a high-melting point metal layer, and formed on a first interlayer insulation film. The high-melting point metal layer is provided to prevent an increase in the resistance value due to the formation of a pn junction formed by the interconnections.