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Logic gate circuit

机译:逻辑门电路

摘要

The logic gate circuit includes an emitter-grounded switching transistor and a pull-up circuit connected to a collector of the switching transistor. The switching transistor is cut when an input signal has a high level and is turned on when the input signal has a low level. A control MIS transistor is connected to a base of the switching transistor and is turned on and off in response to respective low and high levels, of the output terminal of the switching transistor. An input transistor is connected in series with the control MIS transistor and is turned on and off when the input signal is high and low, resepctively.
机译:逻辑门电路包括发射极接地的开关晶体管和连接到开关晶体管的集电极的上拉电路。当输入信号为高电平时,开关晶体管截止;而当输入信号为低电平时,开关晶体管导通。控制MIS晶体管连接到开关晶体管的基极,并且响应于开关晶体管的输出端子的相应的低电平和高电平而导通和截止。输入晶体管与控制MIS晶体管串联,分别在输入信号为高和低时导通和截止。

著录项

  • 公开/公告号KR860003712A

    专利类型

  • 公开/公告日1986-05-28

    原文格式PDF

  • 申请/专利权人 야마모도 다꾸마;

    申请/专利号KR19850007152

  • 发明设计人 다니자와 데쯔 외 1;

    申请日1985-09-27

  • 分类号H03K19/00;

  • 国家 KR

  • 入库时间 2022-08-22 07:34:43

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