1. A method of determining the time-to-fail T of chips having an epitaxial layer and integrating bipolar semiconductor devices likely to have defects resulting from instabilities in the passivation oxide layer of said devices, and at least one IGFET type test structure, which are produced on a manufacturing line, and more particularly, of determining the corresponding burn-in time T50 necessary for 50% chips to be made deficient, characterized in that it includes the steps of : - previous elaboration of the manufacturing line which consists in : selecting a plurality of chip batches produced on the manufacturing line ; computing for each batch from the test structure, coefficients Nss (interface charge density), Neff (equivalent passivation oxide charge) and ND (impurity concentration in the epitaxial layer) ; calculating, for each batch, the value of a reliability function R defined as being equal to the product Nss Neff ND **1/2 and determining for each batch the time-to-fail T such as, for instance, the corresponding time T50 ; plotting curve R=f(T), R=f(T50 ), for instance, the characteristic of the manufacturing line, and - determining the time-to-fail time T of any chip produced on said manufacturing line, which consists in : computing the previously defined coefficients Nss , Neff and ND on the test structure of said chip ; calculating the value of the reliability function R for said chip, and determining the time-to-fail T, T50 , for instance, corresponding to said value through a direct reading of the corresponding value on the previously plotted curve R=f(T).
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