A clock phase adjusting system is provided, including: a scan in/our apparatus, having (n+1) special scan-out latch circuits; a first delay device which selectively outputs an input clock as a delay clock output of a maximum m=2n steps in accordance with an (n) bit selection signal; a second delay device which selectively outputs the input clock signal as the delay clock signals of further minimum 1/2P steps of a minimum step width by the first delay device in accordance with the (P) bit selection signal and which is connected in cascade with the first delay device, so that the delayed clock signals of 1/2P steps are output as the input clock signal by only setting, in the (n+p) scan in/out latch circuits, the selection data for obtaining a delay clock signal.
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