CMOS technique multistage carry ripple adder with two types of adder cells

摘要

A multi-digit carry ripple adder in CMOS technology and having two types of adder cells, in which an inverted carry input signal (Cin) is in each case applied to the adder cells of a first type (I) and a non- inverted carry input signal (Cin) is in each case applied to the adder cells of a second type (II) and in which a non-inverted carry output signal (Cout) is in each case output by the adder cells of the first type and an inverted carry output signal (Cout) is in each case output by the adder cells of the second type. The gate arrangements in each case required are formed in such a manner that the charging of the capacitance of the carry output occurs either via only one transfer transistor 117' or 118' acting as transfer gate or via the series circuit of only two transistors, one of which is in each case contained in gates IIl, II2 (or 13,14) and the second is in each case formed by a transfer gate 117 or 118. Due to the different carry paths, both the binary value "0" and the binary value "1" can be transferred without additional off-state losses. The transfer transistors (7,7',8,8') are not a component of a combination gate within the gate arrangement so that they can be designed to be of lower impedance than the remaining gate transistors. …IMAGE…