Adder cell for a carry ripple adder of the CMOS technique

摘要

a addiererzelle to carry ripple adder in cmos technology, with a gatteranordnung for two variables (a, b), for the evaluation of a u00fcbertragseingangssignals (cin) to the sum of and the u00fcbertragsbildung,each of a eingangsklemme for one of the two variables and a u00fcberu00adtragungseingangssignal and one ausgangsklemme for a summensignal (s) and a u00fcbertragsausgangssignal (court) vorgesenen. on the gatteranordnung is such that the charge capacity of the u00fcbertragsausu00adgangs via a series connection of two transistorgattern (3, 7)4, 8) of a versorgungsspannungsquelle is carried out, and the transistorgatter (3, 7) 4, 8) in a kombinationsgatter are included, so that the one of the transistorgatter (3)4), namely a driving inverter, which is not in the time critical u00fcberu00adtragspfad is inserted, without limitation by the layout geometry significantly niederohmiger than the other transistorgatter (7 / - 8), namely a following transfergatter, read.