PROGRMMING METHOD AND MANUFACTURE OF FLOATING GATE TRANSISTOR, AND STAGGER SPLIT GATE FLOATING GATE MEMORY ARREY, AND STRUCTURE IN CLUDING FLOATING GATE TRANSISTOR

摘要

PURPOSE: To provide a device erasable in a system with a small erase voltage by a method wherein a programming drain voltage for controlling an amount of current which can flow in a drain when programmed is generated from an electric charge pump. CONSTITUTION: A transistor 10 has an N+ source 12, an N+ drain 14, a control gate 16 and a floating gate 18. The transistor 10 is formed within a P+ region 20 for enhancing the programming efficiency. A P-region 21 is formed in a portion 22 of a channel region to reduce a valid threshold voltage of the portion 22. A control gate voltage of waveform as shown in Fig. b is applied to the control gate 16 by a circuit 27, and a voltage having waveform of Fig. a is applied to the drain 14 by a circuit 28. A threshold voltage VT does not reach about 8V before a control gate voltage VCG reaches 8V, so that the transistor 10 is programmed without requiring a drain current of 1μA or higher.