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Program manner and production manner and sutagasupuritsutogeto floating gate memory array of the floating gate transistor and includes the floating gate transistor the structure

机译:浮栅晶体管的编程方式和生产方式以及sutagasupuritsutogeto浮栅存储阵列并包括浮栅晶体管的结构

摘要

A floating gate transistor is programmed by a conventional charge pump providing drain programming current, typically held below about 1 mu A. The drain current can be limited by connecting a resistor between the source and ground, or by limiting the transistor control gate voltage. Instead, a charge pump is coupled to the drain while the control gate is repetitively pulsed. Each time the control gate is pulsed, the transistor turns on, and although the drain is initially discharged through the transistor, some hot electrons are accelerated onto the floating gate, and eventually the floating gate is programmed. The erase gate voltage may be raised to enhance programming efficiency.
机译:浮栅晶体管由常规的电荷泵编程,该电荷泵提供漏极编程电流,通常保持在约1μA以下。可以通过在源极和地之间连接电阻或限制晶体管控制栅极电压来限制漏极电流。取而代之的是,电荷泵耦合到漏极,同时控制栅极被重复地脉冲化。每次对控制栅极施加脉冲时,晶体管都会导通,尽管漏极最初会通过晶体管放电,但仍有一些热电子加速到浮栅上,最终对浮栅进行了编程。可以升高擦除栅极电压以提高编程效率。

著录项

  • 公开/公告号JP2963708B2

    专利类型

  • 公开/公告日1999-10-18

    原文格式PDF

  • 申请/专利权人 UEIFUAA SUKEERU INTEGUREISHON INC;

    申请/专利号JP19890320426

  • 发明设计人 REZA KAZERONIAN;BOAZU EITAN;

    申请日1989-12-09

  • 分类号H01L21/8247;G11C16/06;H01L29/788;H01L29/792;

  • 国家 JP

  • 入库时间 2022-08-22 02:32:49

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