首页> 外国专利> Apparatus and method for implementing precise interrupts on pipelined processor with multiple functional units

Apparatus and method for implementing precise interrupts on pipelined processor with multiple functional units

机译:在具有多个功能单元的流水线处理器上实现精确中断的设备和方法

摘要

An apparatus and method are disclosed for implementing the system architectural requirement of precise interrupt reporting in a pipelined processor with multiple functional units. Since the expense of an interrupt pipeline is warranted only for those interrupts that occur frequently - specifically, those arising from virtual memory management - the apparatus utilizes an interrupt pipeline for frequently occurring interrupts, and a slower, but much less costly, software-based system for precisely reporting the remaining interrupts. The software-based system is facilitated by an instruction numbering and tracing scheme, whereby pertinent information concerning executed instructions is recorded as the instructions pass through the processor pipeline and potentially to other functional units. A software interrupt handler may use this information to isolate and precisely report an interrupt.
机译:公开了一种用于在具有多个功能单元的流水线处理器中实现精确中断报告的系统架构要求的装置和方法。由于仅对频繁发生的那些中断(特别是由虚拟内存管理引起的那些中断)保证了中断流水线的费用,所以该设备将中断流水线用于频繁发生的中断,以及较慢但成本更低的基于软件的系统用于精确报告剩余的中断。指令编号和跟踪方案有助于基于软件的系统,从而在指令通过处理器管道并可能传递到其他功能单元时,记录有关已执行指令的相关信息。软件中断处理程序可以使用此信息来隔离并精确报告中断。

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