Device for the resynchronization of one or more binary data trains at an identical or sub-multiple rate on a synchronous reference clock signal

摘要

the alignment device comprises a signal generator (1) generating clock polyphase clock signals out of phase is also among them, with the reference signal of the clock recovery circuit 110, and in phase 2, 2u02b9), a train of data item.select the version of the clock signal based on the data from being that they have to deal with a double sampling circuit (23, 23u02b9) and a selection circuit (24 24u02b9) clock signals sent from a sequential scanning circuit ( 25, 25u02b9) controlled by a comparator (26 26u02b9)the use of a sampling of the exact values of the data contained in the data and the process data are regenerated by the resampling process values synchronously with the reference clock signal 110.