GATE ARRAY DEVICE HAVING MACRO CELLS FOR FORMING MASTER AND SLAVE CELLS OF MASTER-SLAVE F/F CIRCUIT

摘要

A gate array device forms an arbitrary logic circuit depending on interconnections formed thereon, and comprises a semiconductor chip having an approximate rectangular shape, an input terminal region (11) including a plurality of input terminals formed at a peripheral portion of the semiconductor chip, an output terminal region (12) including a plurality of output terminals formed at a peripheral portion of the semiconductor chip, and a macro cell region (15) including a plurality of macro cells (1, 2) formed at a central portion of the semiconductor chip. The macro cells include first macro cells (1) and second macro cells (2), where each of the first macro cells include a minimum number of elements for forming a master part of a master-slave flip-flop circuit and each of the second macro cells include at least a minimum number of elements for forming a slave part of the master-slave flip-flop circuit. The first macro cells and the second macro cells make macro cell pairs and are regularly arranged within the macro cell region.