首页> 中文期刊>电子科技学刊 >Flash Process-Based Complex Programmable Logical Device with 72 Macro Cells

Flash Process-Based Complex Programmable Logical Device with 72 Macro Cells

     

摘要

A complex programmable logical device(CPLD) based on conventional embedded Flash memory process with 72 macro cells is studied in the paper.Compared with the Flash cell array technology employed by foreign companies, this architecture exhibiting insystem reconfiguration and rapid response was manufactured by low cost fabrication process. The device architecture and critical cell design are also analyzed in detail in the paper. The CPLD was designed by fullcustom ASIC technology and manufactured by 0.35 μm 3P3M Flash process with 72 macro cells and 5 V voltage supply.The measurement results indicate that the devices are able to operate above the frequency of 66.7 MHz with the pin delay less than 10 ns.

著录项

  • 来源
    《电子科技学刊》|2007年第4期|332-335|共4页
  • 作者

    Wen-Chang Li; Ping Li; Wei Li;

  • 作者单位

    State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China (UESTC), Chengdu, 610054, China;

    State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China (UESTC), Chengdu, 610054, China;

    State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China (UESTC), Chengdu, 610054, China;

  • 原文格式 PDF
  • 正文语种 chi
  • 中图分类 真空电子技术;
  • 关键词

    CPLD, Flash process, Macro cell,System frequency.;

  • 入库时间 2023-07-26 00:13:12

相似文献

  • 中文文献
  • 外文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号