CMOS digital clock and data recovery circuit

摘要

An integrated circuit for recovering the clock and data information from phase-encoded serial data. The circuit includes a synchronous delay line coupled to a waveform digitizer and a waveform synthesizer. The waveform digitizer receives and converts the phase- encoded data into a string of bits whose value represent the logic levels of an encoded data at T.sub.p /N intervals where T.sub.p is the reference clock period and N is the resolution of the waveform digitizer. The encoded data may be one of several phase-encoded serial data such as Manchester coding. The digitized output from the waveform digitizer is input to a transition detector, where the locations of the transitions (bit-boundary transitions and bit-center transitions) of the digitized encoded data are extracted. An AND stage comprising N AND gates is coupled to the waveform digitizer and the waveform synthesizer for masking out the bit-boundary transitions and passes the bit-center transitions. The output from the AND stage (a binary word) is coupled to a pair of encoders. The encoders are coupled to an adder and an L-type register which are used for compensating for missing bit-center transitions or for the presence of two bit-center transitions. A digital filter coupled to the L-type register allows the present invention to achieve lockon immediately and to filter out phase jitter. The digital filter is further coupled to a shifter in the waveform synthesizer for synthesizing the clock information of the encoded data on one hand, and for providing mask bits to the AND stage on the other hand. The clock information of the encoded data is synthesized by the shifter in the waveform synthesizer over a digital-to-time domain converter in the waveform synthesizer. Finally, the data information of the phase-encoded serial data is regenerated by a D-type flip flop which receives encoded data over a delayed stage from its D input and also receives the clock information over its clock input.