首页> 外国专利> INTEGRATED-CIRCUIT PACKAGE CONFIGURATION FOR PACKAGING AN INTEGRATED-CIRCUIT DIE AND METHOD OF PACKAGING AN INTEGRATED-CIRCUIT DIE

INTEGRATED-CIRCUIT PACKAGE CONFIGURATION FOR PACKAGING AN INTEGRATED-CIRCUIT DIE AND METHOD OF PACKAGING AN INTEGRATED-CIRCUIT DIE

机译:用于封装集成电路芯片的集成电路封装配置和用于封装集成电路芯片的方法

摘要

A package design configuration for an integrated-circuit die (104) includes a leadframe having its bonding fingers (106) connected to the periphery of an electrically-insulated, heat-conductive substrate (102), formed, for example, of a ceramic material. A number of electrically conductive traces (110), or bonding islands, serve as intermediate bonding locations for shorter bonding wires (112, 116) connecting bonding pads (114) on the integrated-circuit die (104) to the bonding fingers (106) of the leadframe. The integrated-circuit die overlies the conductive traces while still providing an exposed portion of the conductive traces as a respective intermediate attachment area for respective bonding wires. The conductive traces serving as bonding islands are formed by deposition of thin-film material using semiconductor fabrication techniques or by deposition of thick-film material using printing techniques.
机译:用于集成电路管芯(104)的封装设计构造包括引线框架,该引线框架的接合指(106)连接至例如由陶瓷材料形成的电绝缘的导热衬底(102)的外围。 。多个导电迹线(110)或键合岛用作较短的键合线(112、116)的中间键合位置,较短的键合线将集成电路管芯(104)上的键合焊盘(114)连接到键合指(106)引线框架。集成电路管芯覆盖导电迹线,同时仍然提供导电迹线的暴露部分作为用于各个键合线的各个中间附接区域。通过使用半导体制造技术沉积薄膜材料或通过使用印刷技术沉积厚膜材料来形成用作结合岛的导电迹线。

著录项

  • 公开/公告号WO9317455A2

    专利类型

  • 公开/公告日1993-09-02

    原文格式PDF

  • 申请/专利权人 VLSI TECHNOLOGY INC.;

    申请/专利号WO1993US01490

  • 发明设计人 KWON YOUNG IL;LIANG LOUIS H.;

    申请日1993-02-19

  • 分类号H01L23/495;H01L23/498;

  • 国家 WO

  • 入库时间 2022-08-22 05:07:09

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