Pseudo line locked write clock for picture-in-picture video applications

摘要

The PIP clock includes a dividing means for receiving and dividing by a value n, where n is preferably at least six, a fast clock input asynchronous to incoming PIP video information which is n times the speed of the incoming PIP video information. The dividing means includes a cycle reset coupled to the horizontal synchronization signal of the incoming PIP video information, such that the clock signal output is at the rate of the incoming PIP video information and is pseudo line locked to the horizontal synchronization signal. Because the provided pseudo line locked PIP write clock causes data to be written at at most one sixth of a cycle out of sync with the horizontal sync signal when n equals six, and because the PIP image is small (typically one-ninth the original screen size), substantially no visible artifacts are introduced into the PIP image.