Drain bias circuit for high power microwave field effect transistors (FETS) having internal matching

摘要

A drain bias circuit for a high power FET having internal matching (10) for use in an amplifier operating in the microwave range. The circuit is characterized in that it comprises a transmission line constituted by a low impedance microstrip (20) of length &lgr;g/2 at the normal operating frequency, where &lgr;g is the length of the wave guided by the microstrip (20), and two RF choke coils (9a, 9b) which are connected to the center of the above-mentioned low impedance microstrip transmission line (20), thereby splitting the path of the drain current (I.sub.D) into two, which current is thus conveyed to the center of said transmission line, thus making it possible to maintain a load of 50&OHgr; while ensuring that the FET (10) is properly biased.