CONTROLLED-GAIN TRANSISTOR AMPLIFIER WITHOUT DC SHIFT OR SIGNAL PHASE REVERSAL IN LOAD CURRENT

摘要

Signal phase reversal as well as DC shift is avoided in the load current of a controlled-gain transistor amplifier of a type including: first and second transistors (Q1, Q2) connected as a first emitter-coupled differential amplifier; means for applying an input signal voltage (S1) between the base electrodes of the first and second transistors; third and fourth transistors (Q3, Q4) connected as a first current splitter, including an interconnection between the emitter electrodes of the third and fourth transistors to which the collector electrode of the first transistor connects; fifth and sixth transistors (Q5, Q6) as a second current splitter, including an interconnection between the emitter electrodes of the fifth and sixth transistors to which the collector electrode of the second transistor connects; means for applying a control signal voltage (S2) between the base electrodes of the third and fourth transistors and between the base electrodes of the fifth and sixth transistors; means for applying an operating potential to a first interconnection, which is between the collector electrodes of the third and sixth transistors; and means for applying an operating potential to a second interconnection, which is between the collector electrodes of the fourth and fifth transistors, at least one of which means for applying an operating potential includes an output load. Signal phase reversal is avoided by an improvement which comprises: seventh and eighth transistors (Q7, Q8) connected as a second emitter-coupled differential amplifier, means for applying the input signal voltage between the base electrodes of the seventh and eighth transistors, and means for connecting the collector electrodes of the seventh and eighth transistors to separate ones of the first and second connections.