CONTROLLED GAIN TRANSISTOR AMPLIFIER WITHOUT DC SHIFT OR SIGNAL PHASE REVERSAL IN LOAD CURRENT

摘要

Signal phase inversion as well as DC shift in the load current of the gain control transistor amplifier can be eliminated by using a gain control transistor amplifier of the type having the following means. The gain control transistor amplifier, which eliminates signal shifts as well as DC shift, applies an input signal voltage between the first and second transistors connected as first emitter coupled differential amplifiers and the base electrodes of the first and second transistors. The third and fourth transistors connected as first current splitters including means for interconnecting the emitter electrodes of the third and fourth transistors connected to the collector electrodes of the first transistors; Between the fifth and sixth transistors connected as a second current splitter including an interconnection between the emitter electrodes of the fifth and sixth transistors connected to the collector electrode, and the base electrodes of the third and fourth transistors; Control signal voltages between the fifth and sixth transistors, the base electrodes of the third and fourth transistors, and the base electrodes of the fifth and sixth transistors. Means for applying, an operating potential to the first interconnect between the collector electrodes of the third and sixth transistors, and an operating potential to the second interconnect between the collector electrodes of the fourth and fifth transistors. And at least one of the operation potential applying means includes a means including an output load. Signal phase inversion can be eliminated with improved following means. Means for applying an input signal voltage between the seventh and eighth transistors connected as the second emitter coupled differential amplifier, the base electrodes of the seventh and eighth transistors, and the collector electrodes of the seventh and eighth transistors; Signal phase inversion can be eliminated by having means for connecting separately to the first interconnect and the second interconnect.