Gate/source disturb protection for sixteen-bit flash EEPROM memory arrays

摘要

In a flash EEPROM memory array in which a plurality of floating gate field effect transistor memory devices are arranged in rows and columns, in which wordlines are utilized to select rows of such devices and bitlines are utilized to select columns of such devices, in which groups of such devices are arranged in blocks which are independently erasable, and the blocks are divided into sub-blocks for storing lower and upper bytes of words to be stored, apparatus is provided for disabling the wordlines to all high byte sub-blocks when a low byte sub-block is to be programmed, for disabling the wordlines to all low byte sub-blocks when a high byte sub-block is to be programmed, for grounding the sources of all high byte sub-blocks when a low byte sub- block is to be programmed, and for grounding the sources of all low byte sub-blocks when a high byte sub- block is to be programmed.