Lower power CMOS buffer amplifier for use in integrated circuit substrate bias generators

摘要

A complementary MOS buffer and amplifier stage is described herein and is useful for operation in a pump circuit of the type where an integrated circuit substrate is driven above Vcc or below ground potential. This operation serves to minimize parasitic capacitance loading and stabilize MOS device thresholds and consumes very little power. The CMOS buffer and amplifier stage includes first and second complementary input transistors cascaded to drive, respectively, first and second complementary output transistors, and lumped resistance means are connected in series between the first and second complementary input transistors and between the gate electrodes of the first and second complementary output transistors. The resistance means are operative in combination with the capacitance generated at the gate electrodes of the first and second output transistors to generate a circuit time constant that turns one of the first and second complementary output transistors completely off before the other complementary output transistor turns on. This operation completely eliminates crossover currents in the output of the buffer and amplifier stage which would otherwise represent undesirable power losses in the circuit. Advantageously, the resistance means, R, is provided in a preferred embodiment of the invention using one or more long channel MOS transistors connected between the gate electrodes of the first and second complementary output transistors and these devices operate in such a manner as to minimize parasitic capacitance introduced across the resistance means when the buffer and amplifier stage is switched from one to the other of its two conductive states.