PURPOSE:To increase the conversion speed by dividing n-bit digital data into m-number of upper bits and (n-m)-number of lower bits and performing D/A conversion in a set of PWM modulation periods of m-number of upper bits. CONSTITUTION:The first modulation period generating circuit 1 counts a reference clock pulse CLK to generate a PWM modulation period corresponding to m-number of upper bits of n-bit digital data. Ths second modulation period generating circuit 3 generates a PWM modulation period corresponding to (n-m)-bit data. the second modulating circuit 4 counts pulses from the circuit 1 on a basis of (n-m)-bit data to generate a modulation period. A switching circuit 5 selects the outputs of circuits 1 and 4, and the first modulating circuit 2 outputs the period of counting based on upper m-bit data out of the modulation period as a non-modulation period and outputs the remainder as a modulation period.
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