Integratable voltage multiplier for high multiplication factors

摘要

A novel topology of a d.c. voltage multiplier, composed of cascaded sections, which can be described at a system level by a capacitor and a number of controlled switches, wherein, compared with existing topologies, high multiplication factors are achieved with fewer sections, wherein also, if the capacitance values in the various sections are chosen in accordance with a so-called Fibonacci distribution, the low-frequency output resistance of the voltage multiplier is equal to or better than that of existing types having the same multiplication factor and the same sum of all the capacitances, and wherein, if the controlled switches are implemented using MOSFETs, a generally applicable provision is made in which not only the gate voltage, but also the well voltage is controlled.