A method and an arrangement for adapting the rate at which data information is read from a memory to the rate at which data information is written into the memory

摘要

The present invention relates to synchronous (SDH) and plesiochronous (PDH) digital hierarchic systems and to a method and an arrangement for transmitting information between such systems. The inventive arrangement comprises a FIFO register which separates the SDH-system from the PDH-system. An incoming data signal (DATA_1N) arriving at the buffer may contain a so-called bit justification. When a frame includes bit justification which means that a frame includes, one bit more or one bit less than the nominal number of bits. Thus the rate at which information is written into the buffer varies with each frame.;The purpose of the invention is to control the buffer read-out rate, so that read-out will follow the varying rate at which data is read into the FIFO register. Write addresses (WADR) are generated for write-in purposes, while read addresses (RADR) are generated for read-out purposes. According to the invention, the read-out rate is controlled with the aid of a mean value counter (38) which generates mean value addresses (AVADR) . The generated write address and the generated mean address are detected in a first phase detector (33) . When the write addresses (WADR) differ excessively from the mean addresses (AVADR) , as a result of one or more bit justifications, the generation of mean value addresses (AVADR) is then hastened or delayed incrementally, so that the write addresses will pendulate within permissible limits around the mean value addresses. The generated mean value addresses are also used to control the read-out rate. The read address is compared in a second phase detector (40) with a "stuffing value" which relates to the generated mean value address, and if the read address reaches the "stuffing value", this indicates that the buffer read-out rate is too high. When an excessively high readout rate is indicated in the second phase detector, the read-out rate is slowed down.